Comparing circuit



Filed Sep'. 29, 1960 LOW HIGH FIG. I

8 Sheets-Shee'l'. 1

Character CODE BITS A B I 2 4 8 BLANK X X O I 2 8 :I X O 4 8 8 X 0 |I X I 2 8 ale X 4 8 X O I 2 8 O 4 8 :pg I 2 8 4 8 A X 0 B X 0 2 c X O I 2 D X 0 4 E X 0 I 4 F X 0 2 4 G X 0 I 2 4 H X O 8 I X 0 I 8 J X I K X 2 L X I 2 M X 4 N X I 4 0 X 2 4 P X I 2 4 0 X 8 R X 8 S 0 2 T 0 I 2 U 0 4 v 0 I 4 w 0 '2 4 X O I 2 4 Y O 8 Z 0 I 8 ZERO 2 8 I I 2 2 3 I 2 4 4 5 I 4 6 2 4 7 I 2 4 8 B 9 I 8 INVENTORS KELLY B. DAY, Jr.

By RUSSELL G. RI NALDI ATTORNEYS Oct. 15, 1963 K. B. DAY, JR., ETAL 3,107'339 COMPARING CIRCUIT Filed Sep'c. 29. 1960 8 Sheets-Sheet 2 Oct. 15, 1963 K. B. DAY, JR., ETAL 3,l07,339

COMPARING CIRCUIT 8 Sheets-Sheet 4 Filed Sept. 29. 1960 Oct. 15, 1963 K. B. DAY, JR., r-:TAL 3,107,339

COMPARING CIRCUIT Filed Sept. 29, 1960 8 Sheets-Sheet 5 Oct. 15, 1963 K. B. DAY, JR., ETAL 3,107339 COMPARNG CIRCUIT Filed sept. 29, 1980 8 sneets-sheet 8 zoEzooomm .25cm o mmzz w h- Oct. 15, 1963 K. B. DAY, JR., ETAL 3,107,339

COMPARING CIRCUIT 8 Sheets-Sheet 7 Filed Sept. 29, 1960 NDS.

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Oct. 15, 1963 K. B. DAY, JR.. ETAL A3,107,339

COMPARING CIRCUIT Shee'ts-Sheet 8 Filed Sept. 29, 1960 neo Anooo United States Patent O 3,17,339 "CNPARING CiRCUlT Keliy B. Day, Jr., Poughheepsie, and Russell G. Rinaldi, Red Hook, NX., assignors to international Business Machines Corporation, New York, NX., a Corporation of New York Filed Sept. 29, 196%, Ser. No. 53,2% 8 Claims. (Cl. Seth-146.2)

This invention relates to comparing circuits and more particularly zto a comparator which produces outputs indicating that a stored Character is of a higher or lower order than an argument Character.

In many data processing systems it is necessary to make a comparison between two quantities for making high, low or equal determinations. For example, a comparator may be used in a searching unit for finding a document in a file wherein many similar documents or information sheets are arranged in an orderly sequence according to a title or other identifying indicia. Such a file may conftain documents which are arranged 'alphabeticaily in accordance with the names of customers and `a particular document may be mechanically selected and withdrawn by a servomechanism Controlled by la comparison Circuit. The file would be searched by 'comparing the name from a given document with the name being sought and the searc would proceed in one direction or the other dependent upon whether the Compared name was alphabetically higher or lower than the sought after name. Similarly, 'a search might be performed for a documenthaving the same number or other indicia as the number on a given document.

in the prior art, comparison Circuits have been used in conjuuction with such a file search. However, prior art comparing circuits have not been completely satisfactory in some applications. For example, in the application of John A. Stock entitled Comparing Circuit, filed Feb. 16, 1959, Serial No. 793,370 (Docket 18,011), there is shown 'a comparing Circuit for use in conjunction with a data processing system file search. The :comparator of that application is used to Compare 'two signals which 'are encoded in a six-'bit code. In order to make the comparison, the Circuit of that 'application converts the six-bit Code into a modified eight-bit code and uses a binary adder to effect a comparative result. It 'would 'be desirable to provide 'a comparator which operates directly on the sixbit code. Such a Comparator could give high, low or equal outpu'ts and in addition produce information indicative of the alphabetic or numeric characters 'being Compared. Such -a comparator could also produce direct indications of 'blanks in any of the signals being Compared.

In addition, it would be desira'ble to eliminate the adders from the comparator circuitry in order to simplify the circuitry. Accordingly, it is |an important object of the present invention to provide lan improved comparator Circuit which operates directly on two six-bit numbers to provide an indication of whether one number is greater than, equal to, or less than the other signal.

It is another object of the present invention to provide an improved comparator utilizing simple logic Circuits which Can be easily implemented.

It is a further object of the present invention to provide -an improved comparator which produces high, low or equal outputs -in regard to two input siguals and, additionally, produces alphabetic, numeric `and blank identifioations in regard to the input signals.

These and other objects and advantages of the present invention will become more apparent by reading the following specification and appended Claims taken in Conjunction with the drawings in which:

FIG. 1 shows the six-bit Code used in Conjunction with the embodiment shown;

lh' Patented ct. 15, 1963 "ice FIG. 2 shows a 'block diagram of the Comparator of the present invention;

FIG. 3 shows a portion of the special Character and blank decoder of the comparator of the present invention;

FIG. 4 shows another portion of the special Character and blank recognizer of the comparator of the present invention;

FIG. 5 shows the zone 'decoder of the comparator of the present invention;

FIG. 6 shows the numeric equal recognition circuitry of the comparator of the present invention;

FG. 7 shows the non-special Character numeric decoder of lthe Comparator of the present invention; 'and FIG. 8 shows the special 'Character numeric decoder of the Comparator of the present invention.

In accordance with one embodiment of the invention, a Character argument encoded in a six-bit code is compared with stored characters also encoded in a six-bit code. As the argument is compared with each stored Character, the comparator produces 'an output iudicating whether the stored Character is higher than or lower than the arugrnent Character. These higher than 'and lower than outputs 'are used to Control the direction in which the file is to be searched.

Referring to PIG. 1, there is shown the sixebit Code used in conjunction with the shown em'oodiment. In such Well known codes the 48 characters shown in the lefthand column of FIG. 1 'are used presentiy in 'accounting machines and the order shown is such that the uppermost Character, the blank, lies at one end of the scale which extends down through the 47 other characters ending with the number 9. The 48 different characters are coded by placing -an up condition on the lines associated with certain ones of the six-hits iu accordance with well known coding techniques. For example, the blank Condition is indicated Iby 'an up condition of the A bit and the period is represented by an up condition in the A, B, 1, 2 and 8 bits. In this code, the alphabet is divided into three zones 'and the decimal numbers 0 through 9 constitute 'a fourth zone. Within each of these four zones the various letters land numbers may be distinguished from each other by the information carried by the last 'four hits, while the various zones themselves are distinguished from each other by the zone information carried by the first two hits. In making a search through 'a file, it is necessary to determine whether a particular Character in storage is higher than or lower than the ;associated Character of the argument. If the characters are the same, ia vcornparison is made between the next Character of the stored information and the 'associated Character of the argument. The compatison process continues until the comparator produces an output indicating that one of the stored characters is higher or lower than the associated Character of the argument, in which case the search proceeds to another word in storage. The comparator of the subject invention is particul'arly suitable for making such a search.

In describing the 'Circuitry of the present invention, the elements of the Circuitry will be designated by numerals in which the first number indicates the figure number of ,the drawings in which the element appears. In identify'mg the leads which interconnect the elements of the circuitry, the first number indicates the fi-gure number 'on which the leads vappears and the second number indicates lthe figure number to which the lead goes or from which the lead originates.

In 'the following description lines, Carrying signals indicative of the various bits will be designated merely by the number of that bit, that is, bit 1, Z, 4, 8, etc. Lines Carrying signals which are the negation of the bits will be designated by numerals corresponding to the bit but with a 'bar over them, that is, etc. The negation of any signal is obtained 'by the use of a simple inverter as is well known in the art.

Referring to FIG. 2, the argument characters are stored in 'the storage device 20,01 and the records to be searched are indicated generally as 2002. The particular Character which is to be compared with the associated Character of the sto-red record is transferred to the character storage element 2003 designated CR3. 'Ihe 'associated Character of the storage record is transferred to the Character storage element 2004 designated CR1. Both of these characters are connected to a number of decoding circuits which will subsequently be described in detail; CR1 and CR3 are both connected to the special Character and blank decoder 2005. The decoder 2005 recognizes that characters CR1 'and CR3 are blank. If both CRl and CR3 are :not blank, the decoder 2005 produces an output over line 2006 which enables a special Character and blank recognizer 2007 to proceed with the comparison process. CR1 and CR3 are both connected to the special Character and 'blank recognizer 2007. If one of the characters is blank and the other is not blank, the special Character and blank recognizer 2007 produces an output over either line 2008 or 2009 depending upon whether CRl is high or CRl is low. These outputs are connected to OR gates 2010 and 2011, respectively, and the outputs of these OR gates provide the output of the Comparator indicating either that CR1 is high or CR1 is low.

The special Character and blank recognizer 2007 also recognizes whether the two compared characters are special characters. If both CR1 and CR3 are not special characters, the recognizer 2007 produces an output over line 2012 which acts through O'R gate 2013' to enable the zone decoder 2014 to proceed with 'the cornparison process. The line 2012 also enablesa non-special Character numerics decoder 2015 to proceed With the comparison process.

If CR1 and CR3 are special characters, the special Character and blank 'recognizer 2007 produces an output over line 2016 which acts through OR gate 2013 to enable the zone decoder 2014 to proceed With the comparison process and also enables a special Character nur'ne-ric decoder 20,17 'to proceed with lthe recognizing process.

The zone -decoder 20.14 detects whether the zones of the 'two characters are equal. If the zones are not equal, the zone decoder 2014 produces an output over either line 2018 .or 2019 to indicate-either that CR1 is high or CR1 is low. If the zones of CRl and CR3 are equal, the zone decoder 2014 produces an output over line 2020 which enables the nurnerics .equal decoder 2021 to proceed with the comparison. If the numerics of CR1 and CR3 are not equal, the numerics equal decoder 2021 enables the non-special Character numerics decoder 2015 and the special Character numerics decoder 2017 to proceed with the comparison process.

The outputs of the 'special Character and blank reco'gnizer 2007, the zone decoder 2014, the non-special character .numerics decoder 2015, and the special Character numerics decoder 2017 are connected to' both the OR gates 2010 and 201'1. As indicated previously, the output of OR gate 2010 indicates that CR1 is high and an output from OR gate 2011 indicates that CRl is low. The outputs of bothl of these OR gates are connected to an OR Circuit 2023 and the output of this OR Circuit is inverted in an inverter12024, the output of which indicates that CR1 is neither higher nor lower than CR3. Since the inputs to OR gate 2010 'are all down, indicating that CRl is not higher than CR3, the output of OR gate 2010, forming one input of OR gate 2023, is down. Since the inputs to OR gate 2011 are all down, indicating that CR1 is not lower than CR3, the output of OR gate 2011, forming the other input to OR gate '2023, is down. Since both inputs to OR 'gate 2023 are down, the output is down and the output of inverter 2024 is up indicating that CR1 is neither higher than nor lower than CR3. The output 4 of inverter 2024 indicates that the characters just compared are equal and that the next characters of the two words of information being compared should be transferred to Character storage devices 2003 and 2004 for comparison purposes.

Referring to FIG. 3, there is shown logical circuitry which produces signals indicating that CR1 and CR3 are or are not special characters and that CR1 and CR3 are or 'are not blank. The various Combinations of up bits which specify that CR1 is a special Character are detected by the AND gates 3001-3005. For example, if the 1, 2, and 8 bits of CRl are up, and AND gate 3001 is enabled, this AND gate, acting through OR gate 3006 and amplifier 3007 produces an output on output line 3451 indicating that CR1 is a special Character. The output of amplifier 3007 is also connected through an inverter 3008 and another amplifier l3009 to produce a signal on output line 3452 indicating, when this line is up, that CR1 is not a special Character.

' The negation of all of 'the 'bits of CRl are connected to AND gate 3010 directly or through AND gate 3005 to AND gate 3010. When CR1 'is -a blank, the AND gate 3010 is enabled and this AND gate acts through amplifier 3011 to produce a signal on output line 3453 indicating that CR1 is a blank. The output of AND gate 3010 also acts through a'n inverter 3012 and an amplifier 3013 to produce a signal on 3454- indicating that CRl is not a blank.

The circuitry thus far described is duplicated in the lower half of FIG. 3 to produce signals indicating whether CR3 is a special Character or a blank. These signals appear ion line 3455, indicating 'that CRg is 'a special character, line 3456 indicating that CR3 is not a special character, line 3457 indicating that CR3 is a blank, and line 3458 indica'ting that CR3 is not a blank.

Referring to FIG. 4, there is shown circuitry which produces 'a signal over line 4208 indicating that CR1 is low and a signal over line 4209 indicating that CR1 is high. These two signals are connected to OR gates 2010 and 2011, respectively, to provide the signals which control the direction in which the search is to proceed. The signal CR1 special Character numerics low over the line 4851 ror the signal non-special Character numerics lowover line 4751 'act through the OR gate 4001 and the amplifier 4002 to produce -the signal CRl low over line 4203. The signal. CR1 zone low, on line 4551, also acts through O'R gate 4001 and amplifier '4002 to produce the CRl low signal on output line 4208. Similarly, the signals CR1 special Character recognition, on line 435,1 and CR3 not a special Character, on line 4356 are ANDed in AND gate 4003 and the output of this AND gate acts through OR gate 4004, OR gate y4001 and amplifier `4002; to produce the CR1 low signal on output line 4208. Similarly, the signal CR1 blank, on line 4353, and the signal CR3 not bl-ank on line 4358 are ANDed in AND gate 4005. The output of this AND gate acts through the, QR gates 4004 and 4001 and the amplifier 4002 to produce the isignal CR1 low on 'output line 4208. i

T'he signal CR3 special .'character, on line 4355, and t-he signal CR1 not a 'special Character, on line 4352, are ANDed in AND gate '4006. The output of this AND 'gate 4acts through O'R gate 4007 'and OR 'gate 4008 and amplifier 4009 to produce the signal CR1 high on output line 4209. Similarly, the signal CR1 not blan'kr, on line 4354, land signal CR3 blank on line i4357 are ANDed in AND :gate 4010. The output of this AND `gate acts through OR lgate 4007, OR gate 4008, and mplifier 4009 to produce the signal CRl high on line 4209. Each of the signa'ls non-special 'Character numerics high, on line 4752, special Character numer-ics high on line 4852, and zone decoder high on line 4552, acts through theOR gate 4008 and amplifier '4009 to produce the CR1 hi'gh signal on output line 4209. i In order to produce signals indicating that CR1 and CRa are both special characters or CR1 and CR3 are not:`

special characters, AND gates 4911 and 4912 are provided. The signal CRl special character on line 4351 and the signal CR3 special character on line 4355 are both connected to AND gate 4%11. Also connected to AND gate 4911 are the signals CRl not 'blank from line 4354 and the signal CR3 not blank from line 4358. When 'all of these sgnals are up, the AND gate 43m1 is enabled and this AND gate acts through the neon driver 4013 and cathode follower 4-014 to produce the signal CR1 and CRg equal special character on line 4561. In a similar manner, the signals CRa not special Character, CR1 not special character, CRI not blank, and CR3 not b'lank are ANDed in AND gate '4012. The output of this AND gate acts through neon driver 4015 and cathode follower 4016 to produce the signal CRI and CR3 not special characters.

In order to produce signals iudicating that the zones of the vtwo characters being 'compared are equal or not equal, the circuitry of FIG. 5 is provided. The A and B bits of CRl and CR3 are compared with each other in AND gates 5%1 and 55%32, respectively. The negation of the A and B hits of CR1 and CR3 are compared in AND gates 59133 and 50%, respectively. The outputs of AND gates 5961 and 5993 act through OR gate 54305 and cathode follower 55% to enable one leg of the AND circuit 59%7. Simlarly, the outputs of AND gates 5392 and 51304- act through OR gate 5868 and cathode follower 5%09 to enable the second leg of AND gate 5997.

The signal CR1 and CR3 equal special 'character or the sign-al CR1 'and CR3 not equal special character acts through OR gate 5519 and cathode follower 5911 to enable the third leg of AND gate 55197. When AND gate 5%57 `is enabled, the output of this AND gate acts through the grounded grid -amplifier 5012 and the cathode follower 5813 to produce the signal CR1 and CR3 zones equal on output line 5652.

The output of amplifier 5615i is also used to enable the middle leg of -an AND gate 5815. The top :leg of the AND gate 5915 is enabled by the negation of the signal C31 and CR3 zones eq-ual obtained from the output of amplifier Sil. This signal is -inverted in inverter 5016 and the output of this inverter is connected through a cathode follower 5917 to the top leg of AND circuit 5%15.

The Abit of CR3 or the B bit of CR3 acts through OR gate 5518 to enable the second leg of AND gate 5019. The top leg of AND gate 56'19 is enabled by the negation of the CRl and C123 zones equal signal taken from the output of cathode follower 5917. The A bit of CR1 and the negation of the B bit of CR1 enable the other two inputs to AND gate 5319. The output of AND gate 5019 acts through cathode follower 502%, OR gate 51521, and cathode follower 5522, inverter 5923 and `cathode follower 592.4 to enable the third leg of AND gate 5012. When AND gate 5515 is enabled the output acts through cathode follower 5525 to produce the 'signal CR1 low on output line 5451. The output of cathode follower 5022 also enables one leg of AND gate 5il26, the other leg of which is enabled by the signal from the cathode follower 55511. The output of AND gate 5026 acts through the grounded grid :arnplifier '5627 and the cathode follower 5923 to produce the signal CRI high on output line 5452. This signal may 'also be produced by enabling AND gates 56'29 or 503%, each of which can act through OR gate 582.1, cathode follower 5022, AND gate 5926, grounded grid arnplfier 592.7, land cathode follower 5028 to produce the CRI high signal.

In order to Compare the numeric bits of the CR1 and CR3 characters, the circuitry of PIG. 6 is proved. The 1, 2, 4, and 8 bits of CR1 and CR3 are compared in AND gates 6561-6554. The negation of the 1, 2, 4 and 3 bits of CRI and CR3 are compared in AND gates 6%5-6608. The outputs of these AND gates are connected through OR 'gates 6%9-6912 and cathode followers 6013-6916 to enable the inputs to the AND vgate 6917. The output of this AND gate acts through the grounded grid amplifier 6t3l8 and cathode follower 6%.19 to produce the numerics equal signal. The output of cathode follower 6619 is inverted in inverter 6t2l 'and :connected through cathode follower 6921 to enable one leg of AND 'gate 6022. The other leg of AND gate 6822 is enabled by the CRl and CR3 zones equal signal over the line 6552. The output of AND fgate 6622 'acts through cathode follower 6023 to produce the numerics not equal signal on output line 6851.

The ou'tputs of cathode .followers 65-15 and 6016, indicating that the 4 and 8 bits of CR1 and CR3 are equ'al enable AND gate 6526. The output of this AND gate act-s 'through lgrounded grid a-rnplifier 6927 and cathode follower 6028 to produce the signal 8 'and 4 equal on line 6761.

In order to compare the numeric portions of non-special characters, the circuitry of FIG. 7 is provided. The 8 bit of CR1, the negation of the 8 bit of CR3 'and the CR1 not equal to tl signal over line 7854 -are ANDed in the AND gate 7 (till. The output of this AND gate acts through OR gate 7892, Igrounded grid amplifier 7003, 'cathode follower 7864, inverter 7tlil5, and cathode follower 76% to enable one :leg of AND gate 70517. The other two legs of AND gate 7%7 are enabled by the CR1 and CR3 not special chanacter signal over line 7462 and the numerics not equal signal over 'line 7651. The output of AND 'gate 7 M7 acts through cathode follower 7%8 to produce the CR1 low signal over on line 7451.

Similarly, the 4 bit of CR1, the negation of the 3 bit of C33 and the negation of the 4 bit of CRg are ANDed in AND gate 70m, the output of which 'acts through OR gate 7062 to eventually produce the CR1 low signal on line 7451. The CR3 equals tl` signal on line 7353 land the =CR1 not eual to 0 signal on line 7854 are ANDed in AND gate 7610, the output of which may also act through OR Fgate 'N92 to produce the CR1 low signal on line 7451.

The l and 2 bits of CR1 are ANDed in AND gate 7612. The output of fthis AND 'gate acts through OR gate 7013 'and cathode follower 'W14 to enable one leg of AND gate 7015. The other leg of AND gate 7015 is enabled by the 8 yand 4- equ'al si'gnals over line 7661. The output of AND 'gate 7015 may also act through OR gate 70%2 to produce the CR1 low signal on line 7451.

The OR gate 7013 rnay also be enabled by AND gate 7017, the output of which indicates that bit 2 of C31 is up, CRl is not equal to 0, and CR3 is not equal to 2.

The OR gate 7913 may also be enabled by the output of AND gate 7618 which ndicates that the ll bit of CR1 is up, the 2 bit of CR3 is not up, and the l bit of CRE is not up.

In order to produce the CR1 high signal on line 7452, the AND gate '752% is provided. The inputs to this AND gate are enabled by the output of cathode follower 7%4, the numerics not equal signal on line 7651, the CR1 and CRB not special Character signals on 7462, and the zones equal signal on line 7552. The output of AND gate 7020 acts through cathode follower 7921 to produce the CR1 high signal.

In order to Compare the numerics of the special characters, the circuitry of FIG. 8 is provided. The negation of the i, 2, 4 and 8 bits of CR1 are ANDed in AND gate 8001. The output of AND gate S691 acts through OR gate 8962, and cathode follower 8%3, to enable one leg of AND gate 8594. The other inputs to AND gate 8594 are enabled by the CR1 and CR3 equal special Character signals and the numerics not equal signal. The output of AND gate 3%4 acts through the grounded grid amplifier 8%5 and the cathode follower 83% to produce the CR1 high signal on output line 8542. The CR1 high signal is inverted in the inverter 8'1'397, the output of which acts through the cathode follower 8668 to enable one leg of AND gate 81739. The other two inputs to AND gate 8%9 are enabled by the CR1 and CR3 equal special character signal and the numerics not equal signal. The ouput of AND gate 8%9 acts through cathode follower 891% to produce the CR1 low signal on output line 845i.

The OR gate 8%2 may also be enabled by the output of AND gate 8911 which is in turn enabled by the 4 bit of CRI and the 1 bit of CR3. The OR gateV 8,332 may also be enabled by the output of AND gate 8612 which is in turn enabled by the 1 bit of CR3 and the 2 bit of CR1.

In order to produce a signal indicating that CR1 is not equal to the AND gate 8013 is provided. The 2 bit of CRl and the 8 bit of CR1 are ANDed in AND gate il, the output of which is inverted by the inverter 8014 which acts through cathode follower 8015 to produce the CR1 not equal signal on line 8754. Similarly, the 2 bit of CR3 and the 8 bit of CR3 are ANDed in AND gate 8016, the output of which acts through the grounded grid amplifier 8%17 and Cathode folower 8018 to produce the CRg equals t) signal on line 8753.

While a specific embodiment of the invention has been shown and described, it will, of course, be understood that variousother modifications may be made. The appended Claims are, therefore, intended toV cover any such modification within the true spirit and scope of the invention.

What is Claimed is:

l. AA comparator of the type which produces outputs indicating that a stored Character is of a higher or lower order than an argument Character, said characters representing a plurality of special characters, a plurality of alphabetic characters and a plurality of numeric characters each of which includes a predetermined number of zonal bits and a predetermined number of numeric bits, said comparator Comprising a special Character and blank decoder, said special Character and blank decoder producing an output indicating that the argument Character and the stored Character are not blank, a special Character and blank recognizer, said special Character and blank recognizer being enabled by the output of said special character and blank decoder, said special Character and blank recognizer producing first outputs indicating whether the stored Character and said argument Character are special characters and second outputs indicating the relative order of magnitude of said argument and stored characters, a zone decoder, said zone decoder being selectively enabled by the first outputs of said special Character and blank recognizer, said zone decoder producing an output indicating the relative order of magnitude of said stored and said argument characters, said zone decoder producing outputs ndicative of the equality of the zonal bits of the stored and argument characters, a numerics equal decoder, said numerics equal decoder being enabled by the outputs of said Zone decoder, said numerics equal decoder producing an output indicating inequality of the numeric bits of the stored and argument characters, a non-special Character numerics decoder, said non-special Character numerics decoder being enabled by the outputs of said numerics equal decoder and one of said first outputs of said special Character and blank recognizer, said non-special Character numerics decoder producing an output indicating the relative order of magnitude of the numeric bits of the argument and stored characters, a special Character numerics decoder, said special Character numerics decoder being enabled by the other of said first outputs of said special Character and blank recognizer and the outputs of said numerics equal decoder, said special Character numerics decoder producing outputs indicative of the relative order of magnitude of the numeric bits of said argument and said stored characters.

2. A comparator of the type which produces outputs indicating that a stored Character is of a higher or lower order than an argument Character, said characters being encoded in a -bit Code representative of twelve special characters, 26 alphabetic characters and ten numeric characters, said 6-bit Code including two zonal bits and four numeric bits, said comparator comprising a special Character and blank decoder, said special Character and said argument Character being connected to said special Character and the blank decoder, said special Character and blank decoder producing an output indicating that the argument Character and the stored Character are not blank,

a special Character and blank recognizer, said stored character and said argument Character being connected to said special Character and blank recognizer, said special character and blank recognizer being enabled by the output of said special Character and blank decoder, said special Character and blank recognizer producing a first output indicating that both the stored and the argument characters are not special characters, said special Character and blank recognizer producing a second output indicating that said stored Character and said argument Character are both special characters, said special Character and blank recognizer producing third and fourth outputs indicating respectively that the stored Character is of a higher or lower order than said argument Character, a zone decoder, said argument Character and said stored Character being connected to said zone decoder, said zone decoder being selectively enabled by either the first output of said special Character and blank recognizer or said second output of said special Character and blank recognizer, said zone decoder producing an output indicating that the zonal bits of the stored Character are of a higher order that the zonal bits of the argument Character, said Zone decoder producing a second output indicating that the zonal bits of said stored Character are of a lower order than the zonal bits of said argument Character, said zone decoder producingra third output indicating that the zonal bits of the stored and the argument Character are equal, a numerics equal decoder, said argument Character and said stored Character being connected to said numerics equal decoder, said numerics equal decoder being enabled by the third output of said zone decoder, said numerics equal decoder producing an output indicating that the numeric bits of the stored Character are not equal to the numeric bits of the argument Character, a non-special Character numerics decoder, said stored and said argument characters being connected to said non-special Character numerics decoder, said non-special Character numerics decoder being enabled by the output of said numerics equal decoder and the first output of said special Character and blank recognizer, said non-special Character numerics decoder producing a first output indicating that the numeric bits of the stored Character are of a higher order than the numerics bits of the argument Character, said non-special Character numerics decoder producing a second output indicating that the numeric bits of said stored Character are of a lower order than the numeric bits of said argument Character, a special Character numerics decoder, said argument Character and said stored Character being connected to said special Character numerics decoder, said special Character numerics decoder being enabled by the second output of said special Character and blank recognizer and by the output of said numerics equal decoder, said special Character numerics decoder producing a first output indicating that the numeric bits of said stored Character are of a higher order than the numeric bits of said argument Character, said special Character numerics decoder producing a second output indicating that the numeric bits of said stored Character are of a lower order than the numeric bits of said argument Character.

3. The comparator recited in Claim 2 and a first OR Circuit, the third output of said special Character and blank recognizer being connected to said first OR Circuit, the first output of said zonal decoder being connected to said first QR Circuit, the first output of said non-special character numerics decoder being connected to said first OR Circuit, the first output of said special Character numerics decoder being connected to said first OR Circuit, the output of said first OR Circuit indicating that said stored character is of a higher order than the said argument character, a second OR Circuit, the fourth output of said special Character and blank recognizer being connected to said second OR Circuit, the second output of said zonal decoder being connected to said second OR Circuit, the second output of said non-special Character numerics decoder being `connected to said second OR Circuit, the second output of said special Character numerics decoder being connected to said second OR Circuit, the output of said second OR Circuit indicating that the stored Character is of a lower order than the argument Character.

4. The comparator recited in claim 3 and a third OR Circuit, the output of said first OR Circuit being connected to said third OR Circuit, the output of said second OR Circuit being connected to said third OR Circuit, an in verter, the output of said third OR Circuit being connected to said inverter, the output of said inverter indicating that the stored Character is equal to the argument Character.

5. The comparator recited in claim 2 wherein said special Character and blank decoder includes first logic circuitry including first and second AND gates, the numeric bits of said stored Character being connected to said first and second AND gates, the outputs of said first and second AND gates indicating that the stored Character is a special Character, third, fourth and fifth AND circuits, said zonal bits and the negation of said numeric bits of said stored Character being connected to said third, four-th and fifth AND circuits, the output of said third AND Circuit indicating that the stored Character is a special Character, the output of said fifth AND Circuit indicating that said stored Character is a special Character, an OR Circuit, the outputs of said first AND Circuit, said second AND Circuit, said third AND Circuit, and said fifth AND circuits being connected to said OR Circuit, the output of said OR Circuit indicating that said stored Character is a special Character, a sixth AND Circuit, said zonal bits of said stored character being connected to said sixth AND Circuit, the output of said fifth AND Circuit being connected to said sixth AND Circuit, the output of said sixth AND Circuit indicating that the stored Character is blank, and second logic circuitry including Seventh and eighth AND circuits, the numeric bits of said argument Character being connected to said Seventh and eghth AND circuits, the outputs of said Seventh and eighth AND circuits indicating that the argument Character is a special Character, ninth, tenth and eleventh AND circuits, said zonal bits and said numeric bits of said argument Character being connected to said ninth, tenth and eleventh AND circuits, the output of said ninth AND Circuit indicating that the argument Character is a special Character, the output of said eleventh AND Circuit indicating that the argument Character is a special Character, a second OR Circuit, the outputs of said Seventh, eighth, ninth and eleventh AND circuits being connected to said second OR Circuit, the output of said second OR Circuit indicating that said argument Character is a special Character, a twelfth AND Circuit, said zonal bits being connected to said twelfth AND Circuit, the output of said eleventh AND Circuit being connected to said twelfth AND Circuit, the output of said twelfth AND Circuit indicating that said argument Character is a blank.

6. The comparator recited in claim 5 Wherein the special Character and blank recognizer includes a first AND gate, said output indicating that said stored Character is a special Character being connected to said first AND gate, means for negating the output indicating that the argument Character is a special Character, the output of said last-named means being connected to said first AND gate, the output of said first AND gate indicating that the stored Character is of a lower order than the argument Character, a second AND gate, said signal indicating that the stored Character is a blank being connected to said second AND gate, eans for negating the signal indicating that the argument Character is a blank, said last-named means being connected to said second AND Circuit, the

utput of said second AND Circuit indicating that the stored Character is of a lower order than the argument Character, a third AND gate, the signal indicating that the argument Character is a special Character being connected to said third AND gate, means for negating the signal indicating that the stored Character is a special character, said last-named means being connected to said third AND Circuit, the output of said third AND Circuit indicating that the stored Character is of a higher order than the argument Character, a fourth AND Circuit, means for negating the signal indicating that the stored Character is a blank, said last-named means being connected to said fourth AND Circuit, said signal indicating that the argument Character is a blank being connected to said fourth AND Circuit, the output of said fourth AND Circuit indicating that the stored Character is of a lower order than the argument Character, a fifth AND Circuit, the signal indicating that the argument Character is not a blank being connected to said fifth AND Circuit, the signal indicating that the argument Character is a special Character being connected to said fifth AND Circuit, the signal indicating that the stored Character is not a blank being connected to said fifth AND Circuit, the output of said fifth AND Circuit indicating that both the argument character and the stored Character are special characters.

7. The comparator recited in claim 2 wherein said zone decoder includes a plurality of AND gates, the zonal bits of said argument Character and said stored Character being compared in said plurality of AND gates, said pluralit of AND gates producing an output indicating that the zonal bits of the argument Character are equal to the corresponding zonal bits of the stored Character.

8. The comparator recited in claim 2 wherein the numerics equal decoder includes a pluralty of AND gates, the numerics bits of said stored Character being compared With the corresponding numeric bits of said argument character in each of said AND circuits, a numerics equal AND gate, the outputs of said plurality of AND circuits connected to said numerics equal AND gate producing an output indicating that the numeric bits of said store character are equal to the corresponding numeric bits of said argument Character an inverter, the output of said numerics equal Ai\ID gate being connected to said inverter, the output of said inverter being the output of said numerics equal decoder.

References Cited in the file of this patent UNITED STATES PATENTS 2,785,856 Hobbs Mar. 19, 1957 2,885,655 Smoliar May 5, 1959 2,984,824 Armstrong May 16, 1961 

1. A COMPARATOR OF THE TYPE WHICH PRODUCES OUTPUTS INDICATING THAT A STORED CHARACTER IS OF A HIGHER OR LOWER ORDER THAN AN ARGUMENT CHARACTER, SAID CHARACTERS REPRESENTING A PLURALITY OF SPECIAL CHARACTERS, A PLUARLITY OF ALPHABETIC CHARACTERS AND A PLURALITY OF NUMERIC CHARACTERS EACH OF WHICH INCLUDES A PREDETERMINED NUMBER OF ZONAL BITS AND A PREDETERMINED NUMBER O NUMERIC BITS, SAID COMPARATOR COMPRISING A SPECIAL CHARACTER AND BLANK DECODER, SAID SPECIAL CHARACTER AND BLANK DECODER PRODUCING AN OUTPUT INDICATING THAT THE ARGUMENT CHARACTER AND THE STORED CHARACTER ARE NOT BLANK, A SPECIAL CHARACTER AND BLANK RECOGNIZER, SAID SPECIAL CHARACTER AND BLANK RECOGNIZER BEING ENABLED BY THE OUTPUT OF SAID SPECIAL CHARACTER AND BLANK DECODER SAID SPECIAL CHARACTER AND BLANK RECOGNIZER PRODUCING FIRST OUTPUTS INDICATING WHETHER THE STORED CHARACTER AND SAID ARGUMENT CHARACTER ARE SPECIAL CHARACTERS AND SECOND OUTPUTS INDICATING THE RELATIVE ORDER OF MAGNITUDE OF SAID ARGUMENT AND STORED CHARACTERS, A ZONE DECODER, SAID ZONE DECODER BEING SELECTIVELY ENABLED BY THE FIRST OUTPUTS OF SAID SPECIAL CHARACTER AND BLANK RECOGNIZER, SAID ZONE DECODER PRODUCING AN OUTPUT INDICATING THE RELATIVE ORDER OF MAGNITUDE OF SAID STORED AND SAID ARGUMENT CHARACTERS, SAID ZONE DECODER PRODUCING OUTPUTS INDICATIVE OF THE EQUALITY OF THE ZONAL BITS OF THE STORED AND ARGUMENT CHARACTERS, A NUMERICS EQUAL DECODER, 